This card describes an assignment where students apply critical and creative thinking to explore logic gate symbolic representation. Students use Play-Doh to devise a set of novel logic gate symbols and then submit a reflection comparing and contrasting the aesthetics and sensibility of the accepted solutions as well as their own solution. 

The first laboratory experiment in the introduction to combinational logic module of the Digital Logic course introduces students to different gates, Field Programmable Gate Array (FPGA) device as a configurable hardware platform, the development board, and Vivado, which is an example of a Computer Aided Design (CAD) tool that is used to synthesize a Hardware Descriptive Language (HDL) on configurable hardware platforms.

Students modify a simple HDL file multiple times to represent the following seven gates: Not, Or, And, Nor, Nand, Xor, and Xnor. Each time the file is modified, the CAD tool is used to synthesize the hardware on the FPGA device. Then, students use the development board to test the gate that is synthesized on the FPGA device and derive the truth table of the gate by experimentation.

The EML activity that was added to this laboratory assignment challenged students to come up with their own novel symbols of the seven gates, and implement their symbols with Play-Doh. Then, students were asked to:

• Evaluate the accepted logic gate symbols from a sensibility perspective, meaning does it help in expressing the gate’s functionality, and from an aesthetics perspective, which is a personal opinion. 
• Compare their novel symbols with the accepted symbols and comment on why they are more sensible or aesthetically pleasing.
• Reflect on how they took ownership of logic gate symbol representation through this exercise.